完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, Yu-An | en_US |
dc.contributor.author | Peng, Kang-Pin | en_US |
dc.contributor.author | Meng, Yu-Chiao | en_US |
dc.contributor.author | Su, Chun-Jung | en_US |
dc.contributor.author | Li, Pei-Wen | en_US |
dc.contributor.author | Lin, Horng-Chih | en_US |
dc.date.accessioned | 2020-05-05T00:02:22Z | - |
dc.date.available | 2020-05-05T00:02:22Z | - |
dc.date.issued | 2020-04-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.7567/1347-4065/ab650a | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/154179 | - |
dc.description.abstract | We reported an experimental fabrication of double-gated (DG) thin-film transistor (TFT) with IGZO recess-channel using a designer photoresist-based thin-film profile engineering approach. In this approach, an organic shadow mask of photoresist (PR) was formed over a p(+)-Si wafer that was encapsulated by an oxide layer, The lithographically-patterned PR layer is an effective mask for shadowing reactive species during the subsequent deposition steps of IGZO and Aluminum, enabling the formation of IGZO recess-channel and discrete Al source/drain pads at room temperature. The top-gate or DG configurations with the Si substrate serving as the bottom-gate were investigated. The fabricated DG TFTs show significant; improvements in both I-ON and I-OFF as compared with single-gated TFTs. The proposed process scheme is readily applicable to the back-end-of-line of a chip. This work demonstrates the feasibility of IGZO recess-channel TFTs in various gated configurations, enabling a building block for emerging functional devices for More-than-Moore applications. (C) 2020 The Japan Society of Applied Physics | en_US |
dc.language.iso | en_US | en_US |
dc.title | A novel photoresist-based film-profile engineering scheme for fabricating double-gated, recess-channel IGZO thin-film transistors | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.7567/1347-4065/ab650a | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
dc.citation.volume | 59 | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000519630000102 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |