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dc.contributor.authorLee, Cheng-Yenen_US
dc.contributor.authorHuang, Tzu-Pingen_US
dc.contributor.authorChen, Ke-Horngen_US
dc.contributor.authorLin, Ying-Hsien_US
dc.contributor.authorLin, Shian-Ruen_US
dc.contributor.authorTsai, Tsung-Yenen_US
dc.date.accessioned2020-07-01T05:20:36Z-
dc.date.available2020-07-01T05:20:36Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-4-86348-718-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/154288-
dc.description.abstractThis paper proposes a stacked digital low dropout (DLDO) array with three stacked groups to improve security and efficiency, consuming 1/3 of the input current in the prior art. The security is improved by two mechanisms. The advanced encryption standard (AES) engine can be one of point of loads (POLs) hidden in the deeper levels to minimize the disturbance from the AES to the input current. The other is the digital balanced interleave control (DBIC) receives random sources from internal leakage current frequency generator (LCFG) to generate randomly noise current to further hide the current interference caused by the AFS. Due to DBIC anti LCFG techniques, the correlation between input current and AES current is low to 0.006, which is 150 times lower than that of conventional DLDO.en_US
dc.language.isoen_USen_US
dc.titleA High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise Injection and Ultralow Output Ripple for Power-Side Channel Attack Protectionen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 SYMPOSIUM ON VLSI CIRCUITSen_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000531736500111en_US
dc.citation.woscount0en_US
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