標題: | An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications |
作者: | Lin, Yu-Min Wu, Sheng-Tsai Shen, Wen-Wei Huang, Shin-Yi Kuo, Tzu-Ying Lin, Ang-Ying Chang, Tao-Chih Chang, Hsiang-Hung Lee, Shu-Man Lee, Chia-Hsin Su, Jay Liu, Xiao Wu, Qi Chen, Kuan-Neng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Fan-out wafer level packaging;FO-WLP;Process development;Finite element method (FEM);reliability test |
公開日期: | 1-一月-2018 |
摘要: | Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications. |
URI: | http://dx.doi.org/10.1109/ECTC.2018.00060 http://hdl.handle.net/11536/154475 |
ISBN: | 978-1-5386-4998-5 |
ISSN: | 0569-5503 |
DOI: | 10.1109/ECTC.2018.00060 |
期刊: | 2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) |
起始頁: | 349 |
結束頁: | 354 |
顯示於類別: | 會議論文 |