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dc.contributor.authorYan, Jin-Taien_US
dc.contributor.authorYen, Chia-Hengen_US
dc.date.accessioned2020-07-01T05:21:48Z-
dc.date.available2020-07-01T05:21:48Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-1031-8en_US
dc.identifier.issn2472-467Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/154480-
dc.description.abstractIt is known that graphene nanoribbon (GNR) based devices and interconnects can be treated to be better alternative in nano-scale designs. In this paper, given a source pin and a set of target pins inside a GNR grid-based routing plane, based on the consideration of the wirelength and bending delay in graphene nanoribbon, an efficient routing algorithm can be proposed to construct a delay-driven GNR routing tree with minimizing the total wirelength for the target pins. Compared with Das's algorithm [9] on total wirelength and maximum source-to-target delay, the experimental results show that our proposed routing algorithm only uses 8.05% of the extra wirelength to reduce 23.13% of the maximum delay in the construction of a delay-driven GNR routing tree for 6 tested examples on the average.en_US
dc.language.isoen_USen_US
dc.titleConstruction of Delay-Driven GNR Routing Treeen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 17TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department生物資訊及系統生物研究所zh_TW
dc.contributor.departmentInstitude of Bioinformatics and Systems Biologyen_US
dc.identifier.wosnumberWOS:000539647100070en_US
dc.citation.woscount0en_US
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