完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yan, Jin-Tai | en_US |
dc.contributor.author | Yen, Chia-Heng | en_US |
dc.date.accessioned | 2020-07-01T05:21:48Z | - |
dc.date.available | 2020-07-01T05:21:48Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-1031-8 | en_US |
dc.identifier.issn | 2472-467X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/154480 | - |
dc.description.abstract | It is known that graphene nanoribbon (GNR) based devices and interconnects can be treated to be better alternative in nano-scale designs. In this paper, given a source pin and a set of target pins inside a GNR grid-based routing plane, based on the consideration of the wirelength and bending delay in graphene nanoribbon, an efficient routing algorithm can be proposed to construct a delay-driven GNR routing tree with minimizing the total wirelength for the target pins. Compared with Das's algorithm [9] on total wirelength and maximum source-to-target delay, the experimental results show that our proposed routing algorithm only uses 8.05% of the extra wirelength to reduce 23.13% of the maximum delay in the construction of a delay-driven GNR routing tree for 6 tested examples on the average. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Construction of Delay-Driven GNR Routing Tree | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 17TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 生物資訊及系統生物研究所 | zh_TW |
dc.contributor.department | Institude of Bioinformatics and Systems Biology | en_US |
dc.identifier.wosnumber | WOS:000539647100070 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |