標題: A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications
作者: Wang, Shih-Hsing
Hung, Chung-Chih
電機資訊學士班
Undergraduate Honors Program of Electrical Engineering and Computer Science
關鍵字: Switches;Calibration;Power demand;Parasitic capacitance;Capacitors;Transistors;Comparator calibration;kickback noise;parasitic capacitance;sample and hold leakage reduction;SAR ADC
公開日期: 1-Jun-2020
摘要: This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/-0.54 and +0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 mu W at a figure of merit of 4.065 fJ/conv.-step.
URI: http://dx.doi.org/10.1109/TBCAS.2020.2982912
http://hdl.handle.net/11536/154497
ISSN: 1932-4545
DOI: 10.1109/TBCAS.2020.2982912
期刊: IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
Volume: 14
Issue: 3
起始頁: 558
結束頁: 569
Appears in Collections:Articles