完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lai, Bo-Cheng | en_US |
dc.contributor.author | Chen, Chun-Yen | en_US |
dc.contributor.author | Hsin, Yi-Da | en_US |
dc.contributor.author | Lin, Bo-Yen | en_US |
dc.date.accessioned | 2020-10-05T01:59:40Z | - |
dc.date.available | 2020-10-05T01:59:40Z | - |
dc.date.issued | 2020-01-01 | en_US |
dc.identifier.issn | 1556-6056 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LCA.2020.2993040 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/154816 | - |
dc.description.abstract | Sorting is pivotal data analytics and becomes challenging with intensive computation on drastically growing data volume. Sorting on FPGA has shown superior throughput, but the limited in-system memory causes vast data transferring to/from external storage when handling a large dataset. We propose a two-directional sorting (2DSort) architecture which sorts data sequences on both horizontal and vertical directions. 2DSort significantly reduces the costly data transmission by tracking the data on FPGA and writes back the data to external storage when the final sorting position is determined. 2DSort shows average 38.5 percent runtime enhancement in comparison to state-of-the-art bigdata sorting engine on FPGA. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Sorting | en_US |
dc.subject | Field programmable gate arrays | en_US |
dc.subject | Random access memory | en_US |
dc.subject | Distributed databases | en_US |
dc.subject | Computer architecture | en_US |
dc.subject | Throughput | en_US |
dc.subject | Data communication | en_US |
dc.subject | Arithmetic and logic structures | en_US |
dc.subject | data-path design | en_US |
dc.subject | logic arrays | en_US |
dc.subject | system architectures | en_US |
dc.subject | integration and modeling | en_US |
dc.subject | reconfigurable hardware | en_US |
dc.title | A Two-Directional BigData Sorting Architecture on FPGAs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LCA.2020.2993040 | en_US |
dc.identifier.journal | IEEE COMPUTER ARCHITECTURE LETTERS | en_US |
dc.citation.volume | 19 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 72 | en_US |
dc.citation.epage | 75 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000545001600001 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |