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dc.contributor.authorChiang, Chih-Hsuanen_US
dc.contributor.authorKao, Chih-Hengen_US
dc.contributor.authorLi, Guan-Ruen_US
dc.contributor.authorLai, Bo-Cheng Charlesen_US
dc.date.accessioned2014-12-08T15:21:45Z-
dc.date.available2014-12-08T15:21:45Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4244-8499-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/15482-
dc.description.abstractFace detection is one of the fundamental technologies for the future smart objects. However, its computation intensive property thwarts the practice of a real-time application on an embedded device. Parallel processing and many-core architecture have become a mainstream to achieve high performance in the future computing systems. The parallelism of an application needs to be exposed before being exploited by the parallel architecture. This paper performs a comprehensive analysis of the parallelism of a face detection algorithm at different algorithmic levels. This paper has demonstrated that each parallelism level has its own potential to enhance performance, but also imposes different limiting factors to the overall performance. Based on the analysis results and design experience, this paper proposes a multi-staged mixed-level parallelization scheme to retain the performance scalability and avoid the limiting factors. With this scheme, we are able to achieve up to 37.5x performance enhancement on a 64-core system.en_US
dc.language.isoen_USen_US
dc.titleMulti-Level Parallelism Analysis of Face Detection on a Shared Memory Multi-Core Systemen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.citation.spage328en_US
dc.citation.epage331en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000300488600072-
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