-65dB HD3 CMOS TUNABLE OTA WITH MOBILITY REDUCTION COMPENSATION

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Cheng, Shih-Tung	en_US
dc.contributor.author	Chang, Wei-Hsiu	en_US
dc.contributor.author	Hung, Chung-Chih	en_US
dc.date.accessioned	2014-12-08T15:21:45Z	-
dc.date.available	2014-12-08T15:21:45Z	-
dc.date.issued	2011	en_US
dc.identifier.isbn	978-1-4244-8499-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/15484	-
dc.description.abstract	This paper presents a high linearity operational transconductance amplifier (OTA) base on the technique of mobility reduction compensation, which achieves great linearity improvement and has wide input range at low power consumption. The third-order harmonic distortion (HD3) of the OTA is about -65dB at 1MHz for a 1.2-V-pp differential input. The OTA was designed by the TSMC 0.18-mu m CMOS process technology. For 1.8-V supply voltage, the static power consumption is only 0.427mW.	en_US
dc.language.iso	en_US	en_US
dc.title	-65dB HD3 CMOS TUNABLE OTA WITH MOBILITY REDUCTION COMPENSATION	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)	en_US
dc.citation.spage	358	en_US
dc.citation.epage	361	en_US
dc.contributor.department	電機工程學系	zh_TW
dc.contributor.department	Department of Electrical and Computer Engineering	en_US
dc.identifier.wosnumber	WOS:000300488600079	-
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