完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHuang, Ya-Shiueen_US
dc.contributor.authorLiu, Wei-Changen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2014-12-08T15:21:45Z-
dc.date.available2014-12-08T15:21:45Z-
dc.date.issued2011en_US
dc.identifier.isbn978-1-4244-8499-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/15489-
dc.description.abstractIn this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).en_US
dc.language.isoen_USen_US
dc.titleDesign and Implementation of Synchronization Detection for IEEE 802.15.3cen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.citation.spage83en_US
dc.citation.epage86en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000300488600014-
顯示於類別:會議論文