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dc.contributor.authorWang, Shie-Yuanen_US
dc.contributor.authorLi, Jun-Yien_US
dc.contributor.authorLin, Yi-Bingen_US
dc.date.accessioned2020-10-05T02:01:07Z-
dc.date.available2020-10-05T02:01:07Z-
dc.date.issued2020-09-01en_US
dc.identifier.issn1084-8045en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.jnca.2020.102676en_US
dc.identifier.urihttp://hdl.handle.net/11536/155154-
dc.description.abstractAggregating multiple small packets into a large packet provides many advantages. For example, multiple small packets can share a single copy of common Ethernet/IP/UDP headers to reduce the percentage of network bandwidth spent on transmitting headers. In the past, packet aggregation and disaggregation were done by a server CPU or a switch CPU, resulting in low throughputs. In this paper, we design and implement packet aggregation and disaggregation functions in the packet processing pipelines of P4 switches. Our novel designs allow packets with various sizes of payload to be aggregated and disaggregated purely in the data plane of a P4 switch. Experimental results show that the achieved throughputs of our aggregation and disaggregation methods can reach 100 Gbps, which is the line rate of the used P4 switch.en_US
dc.language.isoen_USen_US
dc.subjectPacket aggregationen_US
dc.subjectPacket disaggregationen_US
dc.subjectP4en_US
dc.subjectSDNen_US
dc.titleAggregating and disaggregating packets with various sizes of payload in P4 switches at 100 Gbps line rateen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.jnca.2020.102676en_US
dc.identifier.journalJOURNAL OF NETWORK AND COMPUTER APPLICATIONSen_US
dc.citation.volume165en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000551273600003en_US
dc.citation.woscount0en_US
Appears in Collections:Articles