Full metadata record
DC FieldValueLanguage
dc.contributor.authorLee, Yuan-Shengen_US
dc.contributor.authorHo, Wei-Hsiangen_US
dc.contributor.authorChen, Wei-Zenen_US
dc.date.accessioned2020-10-05T02:01:59Z-
dc.date.available2020-10-05T02:01:59Z-
dc.date.issued2019-08-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2019.2907804en_US
dc.identifier.urihttp://hdl.handle.net/11536/155407-
dc.description.abstractThis paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 2(31)-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm(2). The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.en_US
dc.language.isoen_USen_US
dc.subjectBaud rate CDRen_US
dc.subjectdemultiplexeren_US
dc.subjectintegrating-type receiveren_US
dc.subjectjitter tolerance (JTOL)en_US
dc.subjectoptical receiveren_US
dc.titleA 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recoveryen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2019.2907804en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume54en_US
dc.citation.issue8en_US
dc.citation.spage2243en_US
dc.citation.epage2254en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000560810200014en_US
dc.citation.woscount0en_US
Appears in Collections:Articles