Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, Jack S-Y | en_US |
dc.contributor.author | Lin, Louis Y-Z | en_US |
dc.contributor.author | Huang, Ryan H-M | en_US |
dc.contributor.author | Wen, Charles H-P | en_US |
dc.date.accessioned | 2020-10-05T02:02:22Z | - |
dc.date.available | 2020-10-05T02:02:22Z | - |
dc.date.issued | 2017-01-01 | en_US |
dc.identifier.isbn | 978-1-4503-4972-7 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1145/3060403.3060443 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/155528 | - |
dc.description.abstract | As the manufacturing technology keeps scaling, crosstalk noise induces a greater impact on timing. Although many previous works proposed techniques like timing correlation, functional correlation and path refinement to consider crosstalk noise during static timing analysis, they often suffered from descendant problems including overly-pessimistic timing bound, bad aggressor selection and false paths. Therefore, in this paper, a coupling-aware functional timing analysis tool named CA-FTA is proposed to tame the three problems stated above and to derive a tighter timing bound for the true longest path. Experimental results show that CA-FTA averagely reduces timing bounds of those obtained from crosstalk STA (with path refinement) by 7.26% on several ISCAS'85 and ISPD-2012 benchmark circuits (in particular, by 34.6% for b19). As a result, CA-ETA successfully solves the aggressor-selection problem as well as the false-path problem and relaxes more margins when considering crosstalk noise. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | crosstalk noise | en_US |
dc.subject | coupling wire | en_US |
dc.subject | functional timing analysis (FTA) | en_US |
dc.subject | static timing analysis (STA) | en_US |
dc.title | Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax? | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.doi | 10.1145/3060403.3060443 | en_US |
dc.identifier.journal | PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2017 (GLSVLSI' 17) | en_US |
dc.citation.spage | 251 | en_US |
dc.citation.epage | 256 | en_US |
dc.contributor.department | 電機工程學系 | zh_TW |
dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000568262800046 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |