ESD-Aware Circuit Design in CMOS Integrated Circuits to Meet System-Level ESD Specification in Microelectronic Systems

Abstract

Circuit solution for system-level electrostatic discharge (ESD) protection is presented in this invited talk. To prevent the microelectronic system frozen at the malfunction or upset states after system-level ESD test, on-chip ESD-aware circuit in CMOS ICs should be built to rescue itself from the unknown states for returning normal system operation. A novel concept of transient-to-digital converter is innovatively provided to detect the fast electrical transients during the system-level ESD events. The output digital thermometer codes of the transient-to-digital converter can correspond to the different ESD voltages during system-level ESD tests. The proposed solution has been applied in some display panels to automatically recover the system operations after system-level ESD test.