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dc.contributor.authorChang, Shun-Chiehen_US
dc.contributor.authorLi, Walter Yuan-Hwaen_US
dc.contributor.authorKuo, Yuan-Jungen_US
dc.contributor.authorChung, Chung-Pingen_US
dc.date.accessioned2014-12-08T15:03:02Z-
dc.date.available2014-12-08T15:03:02Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2682-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/1630-
dc.description.abstractLoad instructions usually have long execution latency in a deep processor pipeline, and have significant impact on overall performance. Therefore, how to hide the load latency becomes a serious problem in processor design. The latency of memory load can be separated into two parts: cache-miss latency and load-to-use latency. Previous work which tried to hide the load latency in a deep processor pipeline has some limitations. In this paper, we propose a hardware-based method, called early load, to hide the load-to-use latency with little hardware overhead. Early load scheme allows load instructions to load data from the cache system before it enters the execution stage. In the meantime, a detection method makes sure the correctness of the early operation before the load instruction enters the execution stage. Our experimental results showed that our approach can achieve 11.64% performance improvement in Dhrystone benchmark and 4.97% in average for MiBench benchmark suite.en_US
dc.language.isoen_USen_US
dc.titleEarly Load: Hiding Load Latency in Deep Pipeline Processoren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2008 13th Asia-Pacific Computer Systems Architecture Conferenceen_US
dc.citation.spage124en_US
dc.citation.epage131en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000262465300017-
Appears in Collections:Conferences Paper