Electrical Characteristics of Nanoscale Multi-Fin Field Effect Transistors with Different Fin Aspect Ratio

Abstract

Device characteristics of multiple-fin silicon field effect transistors (FETs) arc sensitive to the channel fin aspect ratio (AR = the fin height / the fin width). In this study, dependence of characteristics on AR for single- and multi-fin FETs arc examined by using a three-dimensional device simulation. The threshold voltage (V(th)) variation of triplefin FET is smaller than that of singlc-fin one clue to a relatively larger effective device width. The triple-fin device with FinFET structure (AR = 2) exhibit rather stable V(th) roll-off characteristics owing to more uniform potential distribution inside the channel. The results of our study show that the driving current, transconductance, gate capacitance of FinFETs are superior to that of tri-gate (AR = 1) and quasi-planar (AR = 0.5) FETs. From the, layout viewpoint, FinFETs has the best layout area efficiency; consequently, to design a device with the subthreshold swing < 70 mV/dec, the layout area of FinFETs is L67 and 1.33 times smaller than those of quasi-planar and tri-gate FETs.