A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with V(dd)/AM and V(dd)/PM Compensations in EER System

doi:10.1109/PACCS.2009.109

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DC 欄位	值	語言
dc.contributor.author	Tsou, Wen-An	en_US
dc.contributor.author	Wuen, Wen-Shen	en_US
dc.contributor.author	Wen, Kuei-Ann	en_US
dc.date.accessioned	2014-12-08T15:24:30Z	-
dc.date.available	2014-12-08T15:24:30Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-0-7695-3614-9	en_US
dc.identifier.uri	http://hdl.handle.net/11536/16999	-
dc.identifier.uri	http://dx.doi.org/10.1109/PACCS.2009.109	en_US
dc.description.abstract	An auto-biasing cascode class-E PA which can compensate the V(dd)/AM and V(dd)/PM distortion resulting from supply modulation has been proposed. The output voltage of auto-biasing control circuit is generated and varied linearly with PA's supply voltage so that the cascode transistor is degenerated into a resistance and the PA's nonlinear distortion can be compensated. The simulation result shows that the distortion is compensated evidently and the system co-simulation demonstrated that system EVM can be improved from -17 to -19dB. Also, the drain efficiency of the PA can be improved 15% within small supply voltage range.	en_US
dc.language.iso	en_US	en_US
dc.subject	Trnsmitters	en_US
dc.subject	class-E power amplifier	en_US
dc.subject	envelope elimination and restoration (EER)	en_US
dc.title	A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with V(dd)/AM and V(dd)/PM Compensations in EER System	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/PACCS.2009.109	en_US
dc.identifier.journal	PROCEEDINGS OF THE 2009 PACIFIC-ASIA CONFERENCE ON CIRCUITS, COMMUNICATIONS AND SYSTEM	en_US
dc.citation.spage	47	en_US
dc.citation.epage	50	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000273677100012	-
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