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dc.contributor.authorWeng, Tsung-Hsien_US
dc.contributor.authorWang, Yi-Tingen_US
dc.contributor.authorChung, Chung-Pingen_US
dc.date.accessioned2014-12-08T15:24:35Z-
dc.date.available2014-12-08T15:24:35Z-
dc.date.issued2011en_US
dc.identifier.isbn978-3-642-24649-4en_US
dc.identifier.issn0302-9743en_US
dc.identifier.urihttp://hdl.handle.net/11536/17044-
dc.description.abstractIn the H.264 video compression standard, the deblocking filter contributes about one-third of all computation in the decoder. With multiprocessor architectures becoming the future trend of system design, computation time reduction can be achieved if the deblocking filter well apportions its operations to multiple processing elements. In this paper, we apply a 16 pixel long boundary, the basic unit for deblocking in the H.264 standard, as the basis for analyzing and exploiting possible parallelism in deblocking filtering. Compared with existing approaches using a macroblock as a basic unit for analysis, a 16 pixel long boundary by having a finer granularity can improve the chances of increasing the degree of parallelism. Moreover, a possible compromise to fully utilize limited hardware resources and hardware architectural requirements for deblocking are also proposed in this paper. Compared with the 2D wave-front method order for deblocking both 1920*1080 and 1080*1920 pixel sized frames, the proposed design gains speedups of 1.57 and 2.15 times given an un-limited number of processing elements respectively. Using this approach, the execution time of the deblocking filter is proportional to the square root of the growth of the frame size (keeping the same width/height ratio), pushing the boundary of practical real-time deblocking of increasingly larger video sizes.en_US
dc.language.isoen_USen_US
dc.subjectdeblockingen_US
dc.subjectparallelizationen_US
dc.subjectmulti-coreen_US
dc.titleExploiting Parallelism in the H.264 Deblocking Filter by Operation Reorderingen_US
dc.typeProceedings Paperen_US
dc.identifier.journalALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, PT I: ICA3PP 2011en_US
dc.citation.volume7916en_US
dc.citation.spage80en_US
dc.citation.epage92en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000307023100008-
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