A digital BIST methodology for spread spectrum clock generators

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chou, Maohsuan	en_US
dc.contributor.author	Hsu, Jenchien	en_US
dc.contributor.author	Su, Chauchin	en_US
dc.date.accessioned	2014-12-08T15:24:42Z	-
dc.date.available	2014-12-08T15:24:42Z	-
dc.date.issued	2006	en_US
dc.identifier.isbn	978-0-7695-2628-7	en_US
dc.identifier.issn	1081-7735	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17149	-
dc.description.abstract	In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small.	en_US
dc.language.iso	en_US	en_US
dc.title	A digital BIST methodology for spread spectrum clock generators	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM	en_US
dc.citation.spage	251	en_US
dc.citation.epage	254	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:000245209300044	-
顯示於類別：	會議論文