標題: 65-nm 160-GHz f(T) RF n-MOSFET intrinsic noise extraction and modeling using lossy substrate de-embedding method
作者: Guo, J. C.
Lin, Y. M.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: RF;noise;lossy substrate;gate length scaling
公開日期: 2006
摘要: A lossy substrate model for accurate simulation of extrinsic noise and a lossy substrate de-embedding method for precise extraction of intrinsic noise have been proven by 80 nm, super-100 GHz f(T) RF nMOS. The method is further applied to 65 nm 160-GHz f(T) nMOS to investigate aggressive gate length scaling effect on P.F noise. The extrinsic noise reveals abnormally weak dependence on gate length scaling even with 50 similar to 60% improvement on f(T) but strong dependence on finger number. The intrinsic noise extracted through lossy substrate de-embedding can consistently reflect the gain in fT and weak dependence on finger number. The NFmin at 10 GHz can be suppressed to 0.5dB for 65 nm nMOS corresponding to an optimized drain current, which is around 0.2 dB improvement over 80 nm devices. Noise suppression due to gate length scaling becomes even more significant in higher current region. The noise reduction is attributed to lower noise resistance (R-n) and real part of optimum source admittance (Re(Y-opt)). The accurate extraction of intrinsic noise provides useful guideline for RF CMOS device design and optimization in terms of speed, power, and noise.
URI: http://hdl.handle.net/11536/17304
ISBN: 0-7803-9573-5
ISSN: 1529-2517
期刊: 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers
起始頁: 349
結束頁: 352
Appears in Collections:Conferences Paper