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dc.contributor.authorOu, Shih-Haoen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorHuang, Chao-Weien_US
dc.contributor.authorKuo, Yu-Tingen_US
dc.contributor.authorChao, Chie-Minen_US
dc.contributor.authorLiu, Chih-Weien_US
dc.contributor.authorJen, Chein-Weien_US
dc.date.accessioned2014-12-08T15:24:57Z-
dc.date.available2014-12-08T15:24:57Z-
dc.date.issued2006en_US
dc.identifier.isbn0-7803-9451-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17335-
dc.description.abstractThis paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.en_US
dc.language.isoen_USen_US
dc.titleA 52mW 1200MIPS compact DSP for multi-core media SoCen_US
dc.typeProceedings Paperen_US
dc.identifier.journalASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGSen_US
dc.citation.spage118en_US
dc.citation.epage119en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000237227500030-
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