完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ou, Shih-Hao | en_US |
dc.contributor.author | Lin, Tay-Jyi | en_US |
dc.contributor.author | Huang, Chao-Wei | en_US |
dc.contributor.author | Kuo, Yu-Ting | en_US |
dc.contributor.author | Chao, Chie-Min | en_US |
dc.contributor.author | Liu, Chih-Wei | en_US |
dc.contributor.author | Jen, Chein-Wei | en_US |
dc.date.accessioned | 2014-12-08T15:24:57Z | - |
dc.date.available | 2014-12-08T15:24:57Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 0-7803-9451-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17335 | - |
dc.description.abstract | This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 52mW 1200MIPS compact DSP for multi-core media SoC | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS | en_US |
dc.citation.spage | 118 | en_US |
dc.citation.epage | 119 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000237227500030 | - |
顯示於類別: | 會議論文 |