標題: High performance context adaptive variable length coding encoder for MPEG-4 AVC/H.264 video coding
作者: Tsai, Min-Chi
Chang, Tian-Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: This paper presents a high-performance VLSI architecture for context adaptive variable length coding (CAVLC) used in the MIPEG-4 AVC/H.264 video coding. Instead of only the coarse-grained 8x8 zero block skipping in the previous design, the proposed design implements the fine-grained zero skipping at the 4x4 block level and the individual coefficient level. The implementation with 0.18um CMOS process just needs average 6.88 cycles for one block coding and costs 11.9K gates when working at 100 MHz. This design saves more than half of cycle count and 48% of area cost when compared with the other designs.
URI: http://hdl.handle.net/11536/17456
ISBN: 978-1-4244-0386-8
期刊: 2006 IEEE Asia Pacific Conference on Circuits and Systems
起始頁: 586
結束頁: 589
Appears in Collections:Conferences Paper