完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lai, Chi-Chen | en_US |
dc.contributor.author | Hwang, Wei | en_US |
dc.date.accessioned | 2014-12-08T15:25:05Z | - |
dc.date.available | 2014-12-08T15:25:05Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-1-4244-0386-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17465 | - |
dc.description.abstract | In this paper, we present a novel FFT/IFFT processor, called reconfigurable mixed-radix (RMR) FFT. It can be easily reconfigured as from 16-point to 4096-point FFT/IFFT with proper mixed-radix algorithm assigned for each mode. The proposed processor is characterized with scalable power-consumption for different FFT/IFFT sizes. Unlike the general pipeline-based architectures which use a larger internal wordlength to achieve a high signal to noise ratio (SNR), our processor keeps the internal wordlength the same as the wordlength of the input data while adopting the block-floating point (BFP) approach to maintain the SNR. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A low-power reconfigurable mixed-radix FFT/IFFT processor | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2006 IEEE Asia Pacific Conference on Circuits and Systems | en_US |
dc.citation.spage | 1931 | en_US |
dc.citation.epage | 1934 | en_US |
dc.contributor.department | 友訊交大聯合研發中心 | zh_TW |
dc.contributor.department | D Link NCTU Joint Res Ctr | en_US |
dc.identifier.wosnumber | WOS:000246793200482 | - |
顯示於類別: | 會議論文 |