完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChen, Wei-Zenen_US
dc.contributor.authorYu, Dai-Yuanen_US
dc.date.accessioned2014-12-08T15:25:07Z-
dc.date.available2014-12-08T15:25:07Z-
dc.date.issued2006en_US
dc.identifier.isbn0-7803-9573-5en_US
dc.identifier.issn1529-2517en_US
dc.identifier.urihttp://hdl.handle.net/11536/17489-
dc.description.abstractThis paper describes the design of a dualband, four-mode Delta-Sigma frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3(rd) order Delta-Sigma modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 mu sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1 MHz offset are about -114 dBc/Hz and -116 dBe/Hz respectively at 5 GHz and 2.5 GHz; frequency bands. Fabricated in a 0.18- mu m CMOS process, the chip size is 1.95 mm(2). The total power consumption is 19.54 mW from a 1.8 V power supply.en_US
dc.language.isoen_USen_US
dc.titleA dual-band four-mode Delta-Sigma frequency synthesizeren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papersen_US
dc.citation.spage225en_US
dc.citation.epage228en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000239086300053-
顯示於類別:會議論文