完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Wei-Zen | en_US |
dc.contributor.author | Yu, Dai-Yuan | en_US |
dc.date.accessioned | 2014-12-08T15:25:07Z | - |
dc.date.available | 2014-12-08T15:25:07Z | - |
dc.date.issued | 2006-01-01 | en_US |
dc.identifier.isbn | 978-0-7803-9572-5 | en_US |
dc.identifier.issn | 1529-2517 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17491 | - |
dc.description.abstract | This paper describes the design of a dualband, four-mode A-E frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3(rd) order Delta-Sigma modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 g sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-mu g in CMOS process, the chip size is 1.95 mm(2). The total power consumption is 19.54 mW from a 1.8 V power supply. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A dual-band four-mode Delta-Sigma frequency synthesizer | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2006 IEEE Radio Frequency Integrated Circuits Symposium | en_US |
dc.citation.volume | en_US | |
dc.citation.issue | en_US | |
dc.citation.spage | 197 | en_US |
dc.citation.epage | 200 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000245137400050 | - |
顯示於類別: | 會議論文 |