標題: Design migration from peripheral ASIC design to area-10 flip-chip design by chip I/O planning and legalization
作者: Chang, Chia-Yi
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: Due to higher I/O count and power delivery problem in deep submicron (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more oppertunities for adoption than traditional peripheral bonding design style in high-performance ASIC and microprocessor designs. However it is hard to tell which technique can provide better design cost edge in usually-concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-IO flip-chip design. It is based on I/O buffer modeling and I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have acheived better area and I/O wirelength in area-IO flip-chip style, compared with peripheral bonding style in packaging consideration.
URI: http://hdl.handle.net/11536/17502
ISBN: 1-4244-0179-8
期刊: 2006 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Proceedings of Technical Papers
起始頁: 147
結束頁: 150
Appears in Collections:Conferences Paper