完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, WZ | en_US |
dc.contributor.author | Hsu, KC | en_US |
dc.date.accessioned | 2014-12-08T15:25:09Z | - |
dc.date.available | 2014-12-08T15:25:09Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-9023-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17539 | - |
dc.description.abstract | 3-dimentional fully-symmetric transformers are proposed and realized in a standard CMOS technology. In contrast to their planar counterparts, the self resonant frequency (f(SR)) of the proposed architecture is improved by 26 % to 53 %, while the chip area is reduced by 40 % to 70 %. The coupling coefficient (K) can be up to 0.77 at 8 GHz in a two turn two layer architecture. Distributed capacitance model (DCM) of the 3-D transformer is also proposed f(SR) evaulation. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | transformer | en_US |
dc.subject | coupling coefficient | en_US |
dc.subject | self resonant frequency | en_US |
dc.title | Miniaturized 3-dimensional transformer design | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE | en_US |
dc.citation.spage | 285 | en_US |
dc.citation.epage | 288 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000234406600061 | - |
顯示於類別: | 會議論文 |