標題: | A 3.33Gb/s (1200,720) low-density parity check code decoder |
作者: | Lin, CC Lin, KL Chang, HC Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2005 |
摘要: | In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm(2) 0.18 mu m silicon area. The other 0.13 mu m chip with the 10.24mm(2) core can further reach a 5.92Gb/s data rate under 1.02V supply. |
URI: | http://hdl.handle.net/11536/17541 |
ISBN: | 0-7803-9205-1 |
ISSN: | 1930-8833 |
期刊: | ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE |
起始頁: | 211 |
結束頁: | 214 |
顯示於類別: | 會議論文 |