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dc.contributor.authorChang, SCen_US
dc.contributor.authorPeng, WHen_US
dc.contributor.authorWang, SHen_US
dc.contributor.authorChiang, THen_US
dc.date.accessioned2014-12-08T15:25:11Z-
dc.date.available2014-12-08T15:25:11Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8838-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/17567-
dc.description.abstractIn this paper, we present an ARM platform-based architecture design for de-blocking filter in H.264. According to statistical analysis, we propose an adaptive transmission scheme to reduce the bus workload. Moreover, we develop a bus-interleaved architecture to reduce the processing latency. As compared to the state-of-the-art designs, our scheme offers 3x to 14x performance improvement. Furthermore, we have proved our design using an ARM emulation board.en_US
dc.language.isoen_USen_US
dc.titleA platform-based de-blocking filter design with bus-interleaved architecture for H.264en_US
dc.typeProceedings Paperen_US
dc.identifier.journalICCE: 2005 INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage293en_US
dc.citation.epage294en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000228036100147-
Appears in Collections:Conferences Paper