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dc.contributor.authorLu, NPen_US
dc.contributor.authorChung, CPen_US
dc.date.accessioned2014-12-08T15:03:12Z-
dc.date.available2014-12-08T15:03:12Z-
dc.date.issued1995-09-01en_US
dc.identifier.issn0129-0533en_US
dc.identifier.urihttp://dx.doi.org/10.1142/S0129053395000233en_US
dc.identifier.urihttp://hdl.handle.net/11536/1758-
dc.description.abstractIn this paper, we study the memory system design for superscalar processing. Benchmarking is used to examine the execution behavior of load/store instructions, such as load/store parallelism and memory load/store port utilization. It is found that the use of only a single load/store port forms a system bottleneck. A superscalar processor benefits from multiple load/store ports and system performance saturates with two load/store ports. The memory system must be carefully designed if multiple load/store ports are supported in a superscalar processor. Thus, we consider the design of the data cache subsystem. The data cache configurations we investigate include multiported cache, multibank cache, and duplicated cache. Through benchmarking, we find that the duplicated cache performs well in most benchmarks. Yet the cost of a duplicated cache is higher. In a superscalar multiprocessing environment, in order to properly maintain memory consistency, we must consider the load/store ordering of the processors. In superscalar processors, the load/store ordering may be in one of three forms: total ordering, load bypassing, and load forwarding. In this research, we conclude that to support the sequential consistency model, the load/store instructions must be totally ordered. Load bypassing and load forwarding are sufficient to support the processor consistency model.en_US
dc.language.isoen_USen_US
dc.subjectsuperscalar processingen_US
dc.subjectload/store porten_US
dc.subjectcacheen_US
dc.subjectmemory consistency modelen_US
dc.titleMemory system design in superscalar processingen_US
dc.typeArticleen_US
dc.identifier.doi10.1142/S0129053395000233en_US
dc.identifier.journalINTERNATIONAL JOURNAL OF HIGH SPEED COMPUTINGen_US
dc.citation.volume7en_US
dc.citation.issue3en_US
dc.citation.spage421en_US
dc.citation.epage443en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department資訊科學與工程研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentInstitute of Computer Science and Engineeringen_US
Appears in Collections:Articles