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dc.contributor.authorLin, YNen_US
dc.contributor.authorLin, CHen_US
dc.contributor.authorLin, YDen_US
dc.contributor.authorLai, YCen_US
dc.date.accessioned2014-12-08T15:25:16Z-
dc.date.available2014-12-08T15:25:16Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7695-2302-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/17644-
dc.description.abstractNetworking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII IGHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.en_US
dc.language.isoen_USen_US
dc.titleVPN gateways over network processors: Implementation and evaluationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalRTAS 2005: 11th IEEE Real Time and Embedded Technology and Applications Symposium, Proceedingsen_US
dc.citation.spage480en_US
dc.citation.epage486en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000228253400046-
顯示於類別:會議論文