Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chiu, Po-Yen	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Tsai, Fu-Yi	en_US
dc.contributor.author	Chang, Yeong-Jar	en_US
dc.date.accessioned	2014-12-08T15:25:20Z	-
dc.date.available	2014-12-08T15:25:20Z	-
dc.date.issued	2009	en_US
dc.identifier.isbn	978-1-4244-2888-5	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17724	-
dc.description.abstract	A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25 degrees C, which is much smaller than that (613 mu A) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.	en_US
dc.language.iso	en_US	en_US
dc.subject	electrostatic discharge (ESD)	en_US
dc.subject	ESD clamp circuit	en_US
dc.subject	gate leakage	en_US
dc.subject	silicon-controlled rectifier (SCR)	en_US
dc.title	Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2	en_US
dc.citation.spage	750	en_US
dc.citation.epage	753	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000272068100123	-
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