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dc.contributor.authorWang, YYen_US
dc.contributor.authorTsai, CJen_US
dc.date.accessioned2014-12-08T15:25:23Z-
dc.date.available2014-12-08T15:25:23Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/17774-
dc.description.abstractNew generation of video codecs typically adopts a sophisticated interpolation filter for sub-pixel motion estimation (ME). For embedded applications, it is crucial to reduce both the memory requirement and the computational complexity for sub-pixel ME. The key observation in this paper is that the interpolation filter for motion estimation and the filter for coding do not have to be the same. By adopting a simpler on-the-fly interpolation filter during ME process and a standard-compliant filter for coding purpose, both memory and complexity can be reduced with very little coding performance degradation. Since Hadamard transformed-SAD is often used in high quality codecs as a better matching measure, we further show that the ME interpolation Mer can be combined with Hadamard transform for efficient VLSI implementation. Initial results show very promising performance of the proposed system.en_US
dc.language.isoen_USen_US
dc.titleAn efficient dual-interpolator architecture for subpixel motion estimationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.citation.spage2907en_US
dc.citation.epage2910en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000232002402250-
Appears in Collections:Conferences Paper