完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, YP | en_US |
dc.contributor.author | Liang, LH | en_US |
dc.contributor.author | Chung, PJ | en_US |
dc.contributor.author | Phoong, SM | en_US |
dc.date.accessioned | 2014-12-08T15:25:23Z | - |
dc.date.available | 2014-12-08T15:25:23Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-8834-8 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17776 | - |
dc.description.abstract | In this paper we propose a semi-blind time domain equalizer (TEQ) design method that maximize SIR (signal-to-interference ratio) in frequency domain for VDSL systems. The proposed method exploits the training symbols in VDSL initialization using an eigen approach. Unlike earlier eigen based TEQ designs, the proposed method does not require the channel impulse response. The TEQ can be obtained by computing an eigenvector of a positive definite matrix that depends only on the averaged received VDSL symbols. Examples will be given to demonstrate that the proposed TEQ design method can effectively shorten the channel impulse response, and achieve very good bit rates with only a small number of training symbols. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A frequency-domain SIR maximizing time-domain equalizer for VDSL systems | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | en_US |
dc.citation.spage | 3163 | en_US |
dc.citation.epage | 3166 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000232002403037 | - |
顯示於類別: | 會議論文 |