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dc.contributor.authorChih, JCen_US
dc.contributor.authorChen, KLen_US
dc.contributor.authorChen, SGen_US
dc.date.accessioned2014-12-08T15:25:24Z-
dc.date.available2014-12-08T15:25:24Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/17780-
dc.description.abstractIn this paper, we improve our previous efficient CORDIC processor design. The improvements consist of two parts: (1) an improved table-lookup rotation scheme with a smaller table than before, and (2) a new efficient on-line table-lookup scheme for scale-factor computations and compensations which is better than the previous non-online design. Combining the improvements with the original efficient rotation angle recoding algorithm and leading-one (or zero) bit detection (for skipping redundant rotations), we obtain a lowiteration and low-complexity COREDC processor architecture. The design is more efficient than the current designs, especially in the iteration count. Simulation shows that for n-bit results, about only n/4 iterations are required. We also designed a 16-bit CORDIC processor based on 0.25 mu m UMC process. Its averaged iteration count is only 4.4 including rotation and scale factor compensations, with a total gate count of 5742 and a maximum operating frequency of 250MHz.en_US
dc.language.isoen_USen_US
dc.titleA CORDIC processor with efficient table-lookup schemes for rotations & on-line scale factor compensationsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.citation.spage3315en_US
dc.citation.epage3318en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000232002403075-
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