標題: RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
作者: Tu, SW
Jou, JY
Chang, YW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: Inductance effects of on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially for global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we first show that the worst-case switching patterns that incur the largest bus delay are quite different while considering RC and RLC effects. ne finding implies that existing encoding schemes based on the RC model might not improve or even worsen the bus delay when inductance effects become dominant. We then propose a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results show that our encoding method can significantly reduce the worst coupling delay of a bus.
URI: http://hdl.handle.net/11536/17785
ISBN: 0-7803-8834-8
ISSN: 0271-4302
期刊: 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
起始頁: 4134
結束頁: 4137
Appears in Collections:Conferences Paper