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dc.contributor.authorChung, SSen_US
dc.contributor.authorLiu, YRen_US
dc.contributor.authorYeh, CFen_US
dc.contributor.authorWu, SRen_US
dc.contributor.authorLai, CSen_US
dc.contributor.authorChang, TYen_US
dc.contributor.authorHo, JHen_US
dc.contributor.authorLiu, CYen_US
dc.contributor.authorHuang, CTen_US
dc.contributor.authorTsai, CTen_US
dc.contributor.authorShiau, WTen_US
dc.contributor.authorSun, SWen_US
dc.date.accessioned2014-12-08T15:25:27Z-
dc.date.available2014-12-08T15:25:27Z-
dc.date.issued2005en_US
dc.identifier.isbn4-900784-00-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/17834-
dc.description.abstractIn this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge out-diffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.en_US
dc.language.isoen_USen_US
dc.subjectstrained-Si devicesen_US
dc.subjectCharge-Pumping(CP)en_US
dc.subjectGated-Diode(GD) methodsen_US
dc.subjectNegative Bias Temperature Instability(NBTI)en_US
dc.titleA new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 Symposium on VLSI Technology, Digest of Technical Papersen_US
dc.citation.spage86en_US
dc.citation.epage87en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000234973100033-
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