完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Li, KSM | en_US |
dc.contributor.author | Lee, CL | en_US |
dc.contributor.author | Su, CC | en_US |
dc.contributor.author | Chen, JE | en_US |
dc.date.accessioned | 2014-12-08T15:25:45Z | - |
dc.date.available | 2014-12-08T15:25:45Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.isbn | 0-7695-2235-1 | en_US |
dc.identifier.issn | 1081-7735 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18184 | - |
dc.description.abstract | The crosstalk fault effects in deep sub-micron VLSI, namely, glitches and the crosstalk-induced delay, are investigated. The origin of their occurrence, relationship and importance in circuit operation are elucidated. It is shown that the crosstalk-induced delay is only superposition of the induced glitch with the original signal delay on the affected victim line; and crosstalk-induced delay is more important in affecting the circuit performance, and should be considered in more details for testing. A scheme which is to detect both types of faults in a unified way by just detecting glitches is proposed and studied considering the manufacture process variation. In this way, detection of crosstalk-induced faults becomes much easier. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A unified approach to detecting crosstalk faults of interconnects in deep submicron VLSI | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | en_US |
dc.citation.spage | 145 | en_US |
dc.citation.epage | 150 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000225878400024 | - |
顯示於類別: | 會議論文 |