A 15b 20MS/s CMOS pipelined ADC with digital background calibration

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Liu, HC	en_US
dc.contributor.author	Lee, ZM	en_US
dc.contributor.author	Wu, JT	en_US
dc.date.accessioned	2014-12-08T15:25:47Z	-
dc.date.available	2014-12-08T15:25:47Z	-
dc.date.issued	2004	en_US
dc.identifier.isbn	0-7803-8267-6	en_US
dc.identifier.issn	0193-6530	en_US
dc.identifier.uri	http://hdl.handle.net/11536/18214	-
dc.language.iso	en_US	en_US
dc.title	A 15b 20MS/s CMOS pipelined ADC with digital background calibration	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS	en_US
dc.citation.volume	47	en_US
dc.citation.spage	454	en_US
dc.citation.epage	455	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.identifier.wosnumber	WOS:000221633800189	-
顯示於類別：	會議論文