完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Deng, CK | en_US |
dc.contributor.author | Yang, SC | en_US |
dc.contributor.author | Tasi, YM | en_US |
dc.date.accessioned | 2014-12-08T15:25:49Z | - |
dc.date.available | 2014-12-08T15:25:49Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.isbn | 0-7803-8262-5 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18263 | - |
dc.description.abstract | Different test structures used to investigate the electrostatic discharge (ESD) robustness of on-glass device in Low Temperature Poly-Si (LTPS) process are proposed in this paper. The transmission line pulse generator (TLPG) is used to monitor the I-V behaviors of on-glass devices in the high-current region, and to evaluate the robustness of those LTPS devices during ESD stress condition. Finally, a successful ESD protection design with P+-i-N+ diodes and a VDD-to-VSS ESD clamp circuit integrated on a LCD panel has been demonstrated with a machine-model (MM) ESD level of up to 275 V, whereas the traditional one only can sustain 100 V MM ESD stress. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Test structures to verify ESD robustness of on-glass devices in UPS technology | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ICMTS 2004: PROCEEDINGS OF THE 2004 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES | en_US |
dc.citation.spage | 13 | en_US |
dc.citation.epage | 17 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000222087700003 | - |
顯示於類別: | 會議論文 |