| 標題: | Design-for-digital-testability 30 MHz second-order Sigma-Delta modulator |
| 作者: | Hong, HC 電控工程研究所 Institute of Electrical and Control Engineering |
| 公開日期: | 2004 |
| 摘要: | A purely digitally testable second-order Sigma-Delta modulator is presented. In the test mode, the input stage of the modulator is reconfigured to accept a repetitive Sigma-Delta modulated bit-stream as its stimulus. The proposed test scheme has a low cost, a high fault coverage, high measurement accuracy, and is able to do the at-speed tests. The experimental results show that the dynamic range measured with the digital stimulus is only 2 dB inferior to that with its analog counterpart. |
| URI: | http://hdl.handle.net/11536/18317 |
| ISBN: | 0-7803-8495-4 |
| 期刊: | PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE |
| 起始頁: | 211 |
| 結束頁: | 214 |
| 顯示於類別: | 會議論文 |

