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dc.contributor.authorHong, HCen_US
dc.date.accessioned2014-12-08T15:25:53Z-
dc.date.available2014-12-08T15:25:53Z-
dc.date.issued2004en_US
dc.identifier.isbn0-7803-8495-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/18317-
dc.description.abstractA purely digitally testable second-order Sigma-Delta modulator is presented. In the test mode, the input stage of the modulator is reconfigured to accept a repetitive Sigma-Delta modulated bit-stream as its stimulus. The proposed test scheme has a low cost, a high fault coverage, high measurement accuracy, and is able to do the at-speed tests. The experimental results show that the dynamic range measured with the digital stimulus is only 2 dB inferior to that with its analog counterpart.en_US
dc.language.isoen_USen_US
dc.titleDesign-for-digital-testability 30 MHz second-order Sigma-Delta modulatoren_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCEen_US
dc.citation.spage211en_US
dc.citation.epage214en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000224961000044-
Appears in Collections:Conferences Paper