標題: | A statistical background calibration technique for flash analog-to-digital converters |
作者: | Huang, CC Wu, JT 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2004 |
摘要: | A new background calibration technique is described to digitally trim the input-referred offset voltage of comparators in a high-speed flash analog-to-digital converters. The polarity of comparator's offset is detected by observing the output code density of a random chopping comparator. Binary feedback is used to adjust the comparator's offset. All calibration processing is performed in the digital domain. thus minimizing the overhead for analog circuitry. Two key design parameters are the comparator's trimming step and the thresholds of a peak detector, which determine the offset's standard deviation and the time constant of the calibration loop. |
URI: | http://hdl.handle.net/11536/18390 |
ISBN: | 0-7803-8251-X |
期刊: | 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS |
起始頁: | 125 |
結束頁: | 128 |
顯示於類別: | 會議論文 |