Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, KB | en_US |
| dc.contributor.author | Hsu, HC | en_US |
| dc.contributor.author | Jen, CW | en_US |
| dc.date.accessioned | 2014-12-08T15:25:57Z | - |
| dc.date.available | 2014-12-08T15:25:57Z | - |
| dc.date.issued | 2004 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/18401 | - |
| dc.description.abstract | This paper presents an efficient VLSI architecture of shape-adaptive discrete cosine transform (SA-DCT) for MPEG-4. The proposed architecture contains a cost-effective 1-D variable-length DCT engine and an auto-aligned transpose memory organization. Compared to other designs for SA-DCT, our architecture requires fewer multipliers whereas has higher throughout. Together with address generators and address pointers, the auto-aligned transpose memory organization can achieve transposing, shifting and aligning simultaneously without saving shape information. When clocking at 66.7 MHz, the proposed architecture has a throughput of 43.83 Mpixels/sec. | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization | en_US |
| dc.type | Proceedings Paper | en_US |
| dc.identifier.journal | 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | en_US |
| dc.citation.spage | 777 | en_US |
| dc.citation.epage | 780 | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.identifier.wosnumber | WOS:000223124000195 | - |
| Appears in Collections: | Conferences Paper | |

