完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Yu-Kun | en_US |
dc.contributor.author | Li, De-Wei | en_US |
dc.contributor.author | Lin, Chia-Chun | en_US |
dc.contributor.author | Kuo, Tzu-Yun | en_US |
dc.contributor.author | Wu, Sian-Jin | en_US |
dc.contributor.author | Tai, Wei-Cheng | en_US |
dc.contributor.author | Chang, Wei-Cheng | en_US |
dc.contributor.author | Chang, Tian-Sheuan | en_US |
dc.date.accessioned | 2014-12-08T15:03:18Z | - |
dc.date.available | 2014-12-08T15:03:18Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-1-60558-115-6 | en_US |
dc.identifier.issn | 0738-100X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/1852 | - |
dc.description.abstract | A 1080p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mu m CMOS technology with an area of 10 mm(2) and 242mW at 145MHz. Compared to the state-of-the-art design targeted at 720p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | H.264 | en_US |
dc.subject | encoder | en_US |
dc.subject | high profile | en_US |
dc.subject | 1080p | en_US |
dc.title | A 242mW, 10mm(2) 1080p H.264/AVC high profile encoder chip | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | en_US |
dc.citation.spage | 78 | en_US |
dc.citation.epage | 83 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000258930200017 | - |
顯示於類別: | 會議論文 |