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dc.contributor.authorLin, TJen_US
dc.contributor.authorYang, THen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:26:16Z-
dc.date.available2014-12-08T15:26:16Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7761-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/18648-
dc.description.abstractThe hardware complexity of digital filters is not controllable by straightforwardly rounding the coefficients to the quantization levels. In this paper, we propose an effective alternative that distributes a pre-defined addition budget to the multiplier-less FIR filters, which takes into account the common sub-expression sharing inside the computations. We successfully integrate a heuristic common sub-expression elimination (CSE) algorithm and the coefficient quantization by successive approximation proposed by Li et al. Besides, we also propose an improved search algorithm for an optimal scale factor to settle the coefficients collectively into the quantization space. Simulation results show that CSE effectively reduces 29.1%similar to31.5% budgets for comparable filter responses. Besides, the improved scale factor exploration helps to find an identical or a better (never worse) quantization result with only 32.67%similar to44.53% run time, whether or not CSE is applied.en_US
dc.language.isoen_USen_US
dc.titleArea-effective FIR filter design for multiplier-less implementationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMSen_US
dc.citation.spage173en_US
dc.citation.epage176en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000184904800044-
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