標題: | An efficient VLIW DSP architecture for baseband processing |
作者: | Lin, TJ Chang, CC Lee, CC Jen, CW 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2003 |
摘要: | The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate - the dramatically growing complexity in the register file (RF), and the poor code density. In this paper, we propose a novel ring-structure RF, which partitions the centralized RF into 2N sub-blocks with an explicit N-by-N switch network for N FU. Each sub-block only requires access ports for a single FU We also propose the hierarchical VLIW encoding with variable-length RISC-like instructions and NOP removal. The ring-structure RF saves 91.88% silicon area and reduces 77.35% access time of the centralized RF. Our simulation. results show that the proposed instruction set architecture with the exposed ring-structure RF has comparable performance with the state-of-the-art DSP processors. Moreover, the hierarchical VLIW encoding can save 32%similar to50% code sizes. |
URI: | http://hdl.handle.net/11536/18722 |
ISBN: | 0-7695-2025-1 |
ISSN: | 1063-6404 |
期刊: | 21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS |
起始頁: | 307 |
結束頁: | 312 |
顯示於類別: | 會議論文 |