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dc.contributor.authorLin, SPen_US
dc.contributor.authorChang, YWen_US
dc.date.accessioned2014-12-08T15:26:26Z-
dc.date.available2014-12-08T15:26:26Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7803-7607-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/18767-
dc.description.abstractWe propose in this paper a novel framework for multilevel routing considering both routability and performance. The two-stage multilevel framework consists of coarsening followed by uncoarsening. Unlike the previous multilevel routing, we integrate global routing, detailed routing, and resource estimation together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. Further, the exact routing information obtained at each level makes our framework more flexible in dealing with various routing objectives (such as crosstalk, power, etc). Experimental results show that our approach obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the previous multilevel routing, the three-level routing, and the hierarchical routing can complete routing for only 3, 0, 3 circuits, respectively. In particular, the number of routing layers used by our router is even smaller. We also have performed experiments on timing-driven routing. The results are also very promising.en_US
dc.language.isoen_USen_US
dc.titleA novel framework for multilevel routing considering routability and performanceen_US
dc.typeProceedings Paperen_US
dc.identifier.journalIEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERSen_US
dc.citation.spage44en_US
dc.citation.epage50en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000179771600007-
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