Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Liu, TM | en_US |
dc.contributor.author | Shieh, BJ | en_US |
dc.contributor.author | Lee, CY | en_US |
dc.date.accessioned | 2014-12-08T15:26:37Z | - |
dc.date.available | 2014-12-08T15:26:37Z | - |
dc.date.issued | 2002 | en_US |
dc.identifier.isbn | 0-7803-7448-7 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18910 | - |
dc.description.abstract | In this paper, the efficient modeling codec architecture for binary shape coding is presented. this novel design includes a memory unit that employs the Address Generation module and the Select & Barrel Shift module to speed up the process of border pixels generation. A simple architecture of the modified modeling unit, which uses a Column-scan map to reduce the number of mux and barrel shifter is proposed. Based on the proposed architecture, it deals with not only context computation of the intra mode but also it of the inter mode on the same hardware architecture. In addition, this design technique is suitable for the context-based arithmetic encode/decode in the whole MPEG4 codec system. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An efficient modeling codec architecture for binary shape coding | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS | en_US |
dc.citation.spage | 316 | en_US |
dc.citation.epage | 319 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000186280700081 | - |
Appears in Collections: | Conferences Paper |