完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, CW | en_US |
dc.contributor.author | Wen, KA | en_US |
dc.date.accessioned | 2014-12-08T15:26:43Z | - |
dc.date.available | 2014-12-08T15:26:43Z | - |
dc.date.issued | 2001 | en_US |
dc.identifier.isbn | 0-7803-7005-8 | en_US |
dc.identifier.issn | 1090-3038 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18992 | - |
dc.description.abstract | A low complexity 3-stage parallel interference cancellation (LCPIC) receiver for DS-CDMA cellular systems is proposed and analyzed in this work. Based on numerical analyses, the power efficiency of the LCPIC receiver is close to that of the 3-stage PIC receiver and better than that of the 2-stage PIC receiver in AWGN with either perfect power control or log-normal power control error. In addition, the near-far resistance of the LCPIC, 2-stage, 3-stage PIC, and SIC receivers are analogous since their performance are undistinguishable in near-far channels. Still more, the computational complexity, which is In terms of the needs of flops per bit decision, of the LCPIC receiver is much less than that of the 3-stage PIC receiver and only a little more than that of the 2-stage PIC receiver. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A low-complexity 3-stage parallel interference cancellation receiver (LCPIC) for DS-CDMA cellular systems | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | IEEE 54TH VEHICULAR TECHNOLOGY CONFERENCE, VTC FALL 2001, VOLS 1-4, PROCEEDINGS | en_US |
dc.citation.spage | 853 | en_US |
dc.citation.epage | 857 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000173938400177 | - |
顯示於類別: | 會議論文 |