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dc.contributor.authorHuang, CWen_US
dc.contributor.authorWen, KAen_US
dc.date.accessioned2014-12-08T15:26:43Z-
dc.date.available2014-12-08T15:26:43Z-
dc.date.issued2001en_US
dc.identifier.isbn0-7803-7005-8en_US
dc.identifier.issn1090-3038en_US
dc.identifier.urihttp://hdl.handle.net/11536/18992-
dc.description.abstractA low complexity 3-stage parallel interference cancellation (LCPIC) receiver for DS-CDMA cellular systems is proposed and analyzed in this work. Based on numerical analyses, the power efficiency of the LCPIC receiver is close to that of the 3-stage PIC receiver and better than that of the 2-stage PIC receiver in AWGN with either perfect power control or log-normal power control error. In addition, the near-far resistance of the LCPIC, 2-stage, 3-stage PIC, and SIC receivers are analogous since their performance are undistinguishable in near-far channels. Still more, the computational complexity, which is In terms of the needs of flops per bit decision, of the LCPIC receiver is much less than that of the 3-stage PIC receiver and only a little more than that of the 2-stage PIC receiver.en_US
dc.language.isoen_USen_US
dc.titleA low-complexity 3-stage parallel interference cancellation receiver (LCPIC) for DS-CDMA cellular systemsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalIEEE 54TH VEHICULAR TECHNOLOGY CONFERENCE, VTC FALL 2001, VOLS 1-4, PROCEEDINGSen_US
dc.citation.spage853en_US
dc.citation.epage857en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000173938400177-
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